1. Field of the Invention
The invention relates generally to a semiconductor device and a method of manufacturing the same. More particularly, the invention relates to a semiconductor device comprising a device isolation film of a trench structure, and a method of manufacturing the same, which can solve reduction of an impurity diffusion layer while securing an insulating characteristic of the device isolation film, when the semiconductor device is higher integrated.
2. Description of the Prior Art
Recently, as the level of integration in the semiconductor device is increased, the length of a gate in a memory cell or a transistor is reduced. Also, the area and depth of the junction of an impurity diffusion layer, e.g. source/drain are reduced. Further, as the semiconductor device is higher integrated, the width and area of a device isolation region for electrically isolating neighboring devices, and a contact region for electrically connecting a lower layer and an upper layer are gradually reduced.
However, the level of integration in the semiconductor device is largely dependent on the manufacture equipments. Also, there is a limit in increasing the level of integration by reducing the area of only some portions of the semiconductor device (for example, gate, impurity diffusion layer or device isolation region) within the same technology. Therefore, there is a trend that the level of integration is not significantly increased but little by little increased within the minimum limit.
Generally, the semiconductor device is designed with the minimum design margin and the minimum design rule in order to satisfy the characteristic of the device within the same technology. Accordingly, it is very difficult to increase the level of integration by reducing only some portions of the semiconductor device (for example, gate, impurity diffusion layer or device isolation region). This is because other processes are made difficult as the area is reduced if the area in some portions of the semiconductor device is reduced.
For example, if the area of the impurity diffusion layer is simply reduced in order to increase the level of integration in the semiconductor device, the minimum design margin required to form the contact region is exceeded. It is thus difficult to secure the contact resistance and to satisfy the leakage current of the junction since the contact plug formed in the contact region is formed in the spacer formed at both sides of the device isolation region or the gate. In other words, as the contact region is reduced due to reduced area of the impurity diffusion layer, there is a mis-aligned phenomenon in a lithography process. Thus, the device isolation film formed in the device isolation region, for example, the device isolation film of the trench structure, etc. is etched by a STI (shallow trench isolation) process, thus increasing the leakage current of the junction. Meanwhile, if the device isolation region is reduced, there occurs a significant problem in the level of integration due to limited lithography technology. Also, as the device isolation region is formed exceeding the minimum design margin, there is a problem that the insulating characteristic of the device isolation film is degraded.